FREE COMPUTER TECHNOLOGY, INC. 80486VESA Processor 80486SX/80487SX/80486SX2/80486DX ODP486/80486DX2/Pentium Overdrive Processor Speed 20/25/33/40/50(internal)/66(internal)MHz Chip Set SiS Max. Onboard DRAM32MB Cache 64/128/256KB BIOS AMI Dimensions 330mm x 218mm I/O Options 32-bit VESA local bus slots (3) NPU Options None [Image] CONNECTIONS Purpose Location Purpose Location External battery JP1 Reset switch JP17 Peripheral power save JP2 & JP3 Turbo LED JP18 Speaker JP15 Turbo switch JP19 Power LED & keylock JP16 32-bit VESA Local SL1, SL2,SL3 bus slots USER CONFIGURABLE SETTINGS Function Jumper Position » CMOS normal operation JP21 pins 2 & 3 closed CMOS memory clear JP21 pins 1 & 2 closed DRAM CONFIGURATION Size Bank 0 Bank 1 1MB (4) 256K x 9 NONE 2MB (4) 256K x 9 (4) 256K x 9 4MB (4) 1M x 9 NONE 8MB (4) 1M x 9 (4) 1M x 9 16MB (4) 4M x 9 NONE 20MB (4) 1M x 9 (4) 4M x 9 32MB (4) 4M x 9 (4) 4M x 9 CACHE CONFIGURATION Size Bank 0 Bank 1 TAG 64KB (4) 8K x 8 (4) 8K x 8 (1) 8K x 8 128KB (4) 32K x 8 NONE (1) 8K x 8 256KB (4) 32K x 8 (4) 32K x 8 (1) 32K x 8 CACHE JUMPER CONFIGURATION Size JP11 JP12 64KB Open Open 128KB pins 1 & 2 closed Closed 256KB pins 2 & 3 closed Closed CPU TYPE CONFIGURATION CPU Type JP7 JP8 80486SX pins 2 & 3 closed Open 80487SX pins 1 & 2, 3 & 4 pins 2 & 3 closed closed 80486SX2 pins 1 & 2, 3 & 4 pins 2 & 3 closed closed 80486DX pins 1 & 2, 3 & 4 pins 1 & 2 closed closed 80486DX2 pins 1 & 2, 3 & 4 pins 1 & 2 closed closed ODP486 (168-pin) pins 1 & 2, 3 & 4 pins 1 & 2 closed closed ODP486 (169-pin) pins 1 & 2, 3 & 4 pins 2 & 3 closed closed Pentium Overdrive pins 1 & 2, 3 & 4 pins 2 & 3 closed closed CPU CLOCK CONFIGURATION CPU Clock JP4 JP5 JP6 20MHz Closed Closed Open 25MHz Closed Open Closed 33MHz Open Closed Closed 40MHz Closed Open Open 50MHz Open Closed Open VESA WAIT STATE/BUS SPEED CONFIGURATION CPU speed Wait states JP13 JP14 <= 33MHz 0 wait states Open Open > 33MHz 1 wait state Closed Closed MISCELLANEOUS TECHNICAL NOTE Note: JP2 & JP3 are used for an optional peripheral card timed power shut-down that is set up in CMOS.