CHICONY, INC. CH-486-33/50 L Processor 80486SX/80487SX/80486DX Processor Speed 20/25/33/50MHz Chip Set OPTI Max. Onboard DRAM 32MB Cache 64/128/256KB BIOS AMI Dimensions 330mm x 218mm I/O Options None NPU Options None [Image] CONNECTIONS Purpose Location Purpose Location External battery J1 Turbo LED JP11 Speaker J17 Reset switch SW1 Power LED & keylock J18 Turbo switch SW2 USER CONFIGURABLE SETTINGS Function Jumper Position » CMOS memory normal operation JP1 pins 2 & 3 closed CMOS memory clear JP1 pins 1 & 2 closed » Monitor type select color JP2 Closed Monitor type select monochrome JP2 Open DRAM CONFIGURATION Size Bank 0 Bank 1 1MB (4) 256K x 9 NONE 2MB (4) 256K x 9 (4) 256K x 9 4MB (4) 1M x 9 NONE 5MB (4) 256K x 9 (4) 1M x 9 8MB (4) 1M x 9 (4) 1M x 9 16MB (4) 4M x 9 NONE 20MB (4) 1M x 9 (4) 4M x 9 32MB (4) 4M x 9 (4) 4M x 9 CACHE CONFIGURATION Size Bank 0 Bank 1 TAG 64KB (4) 8K x 8 (4) 8K x 8 (1) 8K x 8 128KB (4) 32K x 8 NONE (1) 32K x 8 256KB (4) 32K x 8 (4) 32K x 8 (1) 32K x 8 CACHE JUMPER CONFIGURATION Size JP3 JP4 JP6 JP7 64KB pins 2 & 3 Open Open Open closed 128KB pins 1 & 2 Closed Closed Open closed 256KB pins 2 & 3 Closed Closed Closed closed CPU TYPE CONFIGURATION Type JP8 JP9 JP10 80486SX pins 1 & 2 Closed pins 1 & 2 closed closed 80487SX pins 2 & 3 Open Open closed 80486DX pins 1 & 2 Closed pins 2 & 3 closed closed CPU SPEED CONFIGURATION Type JP12 20MHz pins 2 & 3 closed 25MHz pins 2 & 3 closed 33MHz pins 2 & 3 closed 50MHz pins 1 & 2 closed